The present disclosure relates to solid-state image capture devices. In particular, the present disclosure relates to a solid-state image capture device that is capable of avoiding a phenomenon that a pixel that is supposed to provide a white signal when excessive light is incident on the pixel is determined to exhibit a white signal (this phenomenon is called a “black sun effect”).
In CMOS (complementary metal-oxide semiconductor) image sensors, the “black sun effect” occurs (this effect is referred to as a “black sinking effect” in Japanese Unexamined Patent Application Publication No. 2007-195033 and is referred to as “blackening effect” in Japanese Unexamined Patent Application Publication No. 2008-67344). The term “black sun effect” refers to the phenomenon that, when very strong light, such as sunlight, is incident on a pixel, an output signal becomes absent suddenly and a portion that is supposed to provide a white signal is recorded as a black signal. Japanese Unexamined Patent Application Publication Nos. 2007-195033 and 2008-67344 discloses technologies for addressing the phenomenon.
In Japanese Unexamined Patent Application Publication No. 2007-195033, a clamp power source is connected to a so-called “correlated double sampling circuit” via a clamp transistor and the correlated double sampling circuit has a clamp capacitor for clamping a voltage output from a pixel via a vertical signal line. Immediately after the pixel is reset, the clamp transistor is turned on to thereby clamp an output voltage of the vertical signal line to the clamp capacitor with reference to the clamp voltage, and in other periods, the clamp transistor is turned off to thereby clip the connection node of the clamp transistor and the clamp capacitor.
In Japanese Unexamined Patent Application Publication No. 2008-67344, a clip circuit is connected to a vertical signal line. This clip circuit does not vary the voltage of the vertical signal line when the voltage of the vertical signal line is higher than a predetermined voltage (VCLIP1) and performs adjustment so that the voltage of the vertical signal line becomes equal to the predetermined voltage (VCLIP1) when the voltage of the vertical signal line is lower than the predetermined voltage (VCLIP1).